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Engineering Manager (SoC Verification)

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  • Location Singapore
  • Job Type Permanent
  • Reference BH-763-3
Key Responsibilities:
  • Execute project on time and deliver results in SoC verification sign-off, AMS verification, functional safety verification and functional test patterns.
  • Build and develop competencies and methodologies in SoC verification and pattern development.
  • Engage externally with Suppliers and/or industry consultants to collect benchmarking data/knowledge and ensure this information feeds into Manufacturing Leadership Team (MLT) strategies; Leverage this knowledge/data to drive priorities and close gaps in performance and feed into equipment roadmaps.
  • Drive company Max Outs, Value Engineering and Sustainability programs.
  • Undertake a technical leadership position in Digital and Analog-Mixed Signal Verification at SOC.
  • Execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements.
  • Execute the verification plan by developing C/C++ testcases and System Verilog/UVM testbench components and by integrating 3rd part VIP components.

Key Requirements:

  • Master’s / Bachelor’s in Electrical / Electronic Engineering or Computer Science with min 15 years of experience in semiconductor design/verification.
  • Current or previous Director or Principal Engineer (or above) experience in MNC organizations
  • Solid technical background in microcontroller SoC Verification and pattern development
  • Strong understanding of Analog/Mixed Signal circuits.
  • Understand the usage of tools like Virtuoso, Xcelium, Simvision and Waveview.
  • Hands-on experience in writing Verilog-A/MS and Real Number Models and building SPICE test benches at Block and Fullchip Level.
  • Hand-on experience in building the COSIM/ Mixed-signal verification environment.
  • Implement mixed-signal test-benches in Cadence Virtuoso and/or Verilog-AMS/System Verilog to apply stimulus and checks.
  • Exposure to version-controlling (eg, Git/Bitbucket, Clearcase, CVS, SVN) and bug-management schemes
  • Experience in UVM-AMS is a plus.
If you would like to apply for this position or would like to understand more about this role, please send your resume to for a confidential discussion.